Compiler Optimizations for Network Processors
Mr. Xiaotong Zhuang
Thursday, January 19, 2006
1:30PM - CSB-232
Abstract
The dramatic growth of Internet applications has motivated the need for a new category of embedded processors called Network Processors (NPs). NPs have fast processing speed and specialized hardware support for network applications. In this talk, I will address my research on compiler optimizations for Intel's IXP network processor. Due to resource limitations, registers are extremely precious on this network processor. To exploit the independence among network packets, IXP is heavily multi-threaded. Register file is specially designed such that the two source operands of any instruction must come from different banks. To speedup packet processing, context switches are extremely lightweight i.e. only the PC is saved. This design raises two problems: 1) how to assign register banks to source operands to avoid unduly running out of registers; 2) how to assign registers across threads in order to maximize the utilization of hardware resources. For the first problem, we present three different approaches for performing register allocation as well as bank assignment. For the second problem, we found that even if registers are not protected across context switches, some registers can still be shared across threads as long as those registers are not used across context switch boundaries. This leads to big savings on the precious register resource, which in turn contributes to speedup as some memory accesses are converted into register references. In the development tools Intel used to ship, there was no support for active register allocation and the assembler used to quit when it cannot find enough registers. Some version of this work was later incorporated into Intel's newly developed IXP compiler.
Short Bio
Xiaotong Zhuang is a doctoral student in the Computer Science department
of Georgia Institute of Technology. Xiaotong also holds an BE degree in
EE from Shanghai Jiaotong Univervisty, and two MS degrees in CS from
Shanghai Jiaotong University and Georgia Institute of Technology
respectively. His main areas of interest are Compilers, Embedded Systems
and Network Processors, Computer Security and Secure Architecture. He
has a minor interest in Parallel and Distributed Systems and Computer
Architecture. During his PhD study, he has conducted researches in many
emerging topics such as power-aware computing, network processors,
secure architectures. As a result of this endeavor, he has published
over 20 papers in conferences and journals.
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