
Beyond Scaling - Realizing Value Through the Integration of Memory and Autonomic Chip Features
Dr. Subramanian S. Iyer
Abstract
Short BioSubramanian S. Iyer obtained his B.Tech in Electrical Engineering at the Indian Institute of Technology, Bombay in 1977, and his M.S. and Ph.D. in Electrical Engineering at the University of California at Los Angeles in 1978 and 1981 respectively. He joined the IBM T. J. Watson Research Center in 1981 and was manager of the Exploratory Structures and Devices Group till 1994, when he founded SiBond LLC to develop and manufacture Silicon-on-insulator materials. Since 1997 he has been with the IBM Microelectronics Division, Semiconductor Research and Development Center, where currently, he is a Distinguished Engineer and manages 90nm and 45nm bulk logic development as well as the embedded DRAM and autonomic chip projects. Dr. Iyer has received a Corporate award and three Outstanding Technical Achievement awards at IBM for the development of the Titanium Salicide process, the fabrication of the first SiGe Heterojunction Bipolar Transistor and the development of embedded DRAM technology. He holds over 35 patents and has received 18 Invention Plateau awards. He received the Distingushed Aluminus award from the Indian Institute of Technology, Bombay in 2004. Dr. Iyer has authored over 150 articles in technical journals and several book chapters and co-edited a book on bonded SOI . Dr. Iyer is a Fellow of IEEE.
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