Low-cost Built-In Self-Test Architecture for Embedded Cores Test

Dr. Mansour Hanna Assaf
Thursday, November 10, 2005
11:00AM - ENG II 202

Abstract


System-on-Chip ( SoC ) is revolutionizing the electronics industry. These super chips will power the next generation of cell phones, multimedia devices and PC graphics chipsets. SoC is a technology that focuses on integrating as many functions of different chips as possible into one single chip. SoC designers incorporate pre-designed and pre-verified models of complex functions known as intellectual property ( IP ) cores or virtual components in a single chip to provide full functionality for an application. A core-based SoC may contain combinations of IP cores for on-chip functions such as microprocessors, audio and video controllers, 2D and 3D graphics controllers, large memory arrays, modems etc. These cores are reusable blocs that have been optimized for performance implying lower design cost; they are generally available in either high-level description language ( HDL ), or transistor-level layout.

Because of the increasing integration of IP cores and the use of embedded systems in SoC, the design complexity of SoC has increased dramatically and is expected to increase continuously at a very fast rate; silicon complexity quadruples every three years. Due to the use of various IP cores from multiple vendors, the SoC design may contain a very high level of integration complexity, design verification, and test issues. These chips are far too complex to be tested by traditional methods. A combination of test methodologies is used to test the individual IP cores, such as a logic built-in self-test, memory built-in self-test, full-scan test, boundary scan test, functional test, etc. In this seminar, I address SoC testing in general and the design of efficient support hardware for built-in self-testing ( BIST ) in particular.

In this context, I will present space compaction techniques, developed and implemented in hardware and software, for particular use in IP core based systems which facilitate designing such circuits using compact or pseudorandom test sets, with the target objective of minimizing the storage requirements for the core under test ( CUT ), reduce test data volume, testing time, and test power consumption simultaneously, while maintaining the fault coverage information. The proposed techniques guarantee simple low-cost design with high or full fault coverage, with maximal compaction ratio, low testing time, and acceptable area overhead.

I will also present a Built-In Self-Test technique for testing the analog circuitry of a mixed-signal IP core. Oscillation-based Built-In Self-Test is a promising testing method for analog cores which neither requires a stimulus generator nor a complex result analyzer. Simulation result shows that the proposed technique allows obtaining high fault coverage. Also this technique requires low area overhead. I will conclude the seminar with a discussion of related and possible future research works.

Short Bio


Mansour Hanna Assaf received his Honours degree in applied physics from the Lebanese University in Beirut, Lebanon in 1989, and B.A.Sc., M.A.Sc., and Ph.D. degrees in electrical engineering from The University of Ottawa, Ottawa, ON, Canada, in 1994, 1996, and 2003 respectively. He afterwards has been associated with the Sensing and Modeling Research Laboratory of the University of Ottawa as a Research Fellow. His research interests include computer architecture, and fault diagnosis in digital and analog systems, specially embedded systems including system-on-chip. He published 12 Journal papers and over 19 conference articles in the area of fault diagnosis in digital and analog systems. He is a member of the IEEE , and of the Canadian Mathematical Society.

He served as a session co-chair member of a number of international conferences on computing techniques and has been a reviewer of several internationally learned journals such as IEEE Transactions on Instrumentation and Measurement, and IASTED Journal of Computers and Applications.