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EECS Distinguished Seminar Series
Semiconductors: From Concept to Market
Front and Back End

Mr. James Norum and Dr. Roger Quon
Friday, April 20, 2007
10:00AM ~ 12:00PM, Harris Center 125

Abstract


In the fascinating world of semiconductor technology development our literature and lectures naturally focus on fundamental research and early feasibility proof for future potential applications in industry. New breakthroughs and future plans for materials research, strain engineering, and technology scaling hold our attention, as they should. This talk, however, will focus on what happens to yesterday’s headlines once an idea gains acceptance as generally feasible, and industry commits to bringing it to market. Conversion of the basic building blocks into a fully integrated, yieldable process flow often presents unexpected challenges to Process Integration teams in industry. Process assumptions, process windows, and process and equipment variability in the “front end of line (FEOL)” and “back end of line (BEOL)” will be studied and discussed, in order to provide a view of the process development cycle that leads to revenue producing products.

This workshop will also discusses the evaluation of Chemical Mechanical Polish (CMP) -induced topography on BEOL, low-k (k = 3.0) interlayer dielectrics (ILD) in 65nm technology. Optimization of the CMP process to minimize both global topography across the wafer and local topography within the reticle field can be challenging as it must be integrated within the process tolerances of lithography. Three different chip designs from a 65nm, 9-level metal build technology are considered.

Short Bio


James "Chip" Norum is the Manager of the 45nm SOI FEOL Process Integration group at the IBM Semiconductor Research and Development Center (SRDC) in East Fishkill, New York. He obtained his BS in Electrical Engineering from Yale University in 1987 and his MEng in Electrical Engineering from Cornell University in 1989. Mr. Norum joined IBM in 1987 and worked on process integration issues related to advanced bipolar transistor technology. Since 2000 he has been involved in the process development of five generations of bulk embedded DRAM, and currently manages the SOI CMOS process integration effort at IBM.

Roger Quon is the Manager of the Advanced Foundry BEOL Process Integration group at the IBM SRDC in East Fishkill, New York. He obtained his BS in Chemical Engineering from the University of Alberta in 1992 and his PhD in Chemical Engineering from the University of Pennsylvania in 1999. Dr. Quon joined IBM in 2000 as a process engineer for flip-chip interconnects technology. In 2005, Dr. Quon moved closer to the transistor level, by joining the Advanced Foundry BEOL Integration team, which he now manages.

Free Lunch @ noon!

for additional information contact Ravi Todi: rtodi@mail.ucf.edu 407-882-2298

Presented by AVS and IEEE Student Chapters of UCF
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