Unfortunately, high-performance parallel programming is hard, time- consuming, and error-prone. To amortize the cost of parallelization, many programmers choose to do so incrementally. Typically, the most promising loops/ regions of a program are identified through profiling. A subset of these regions are then parallelized, and the rest of the application is left as future work. Over time, more effort is spent on portions of the remaining code. As a result of this "pay-as-you-go" approach, the complexity (and cost) associated with software parallelization can be amortized over time.

We envision a CMP-dominated future where a diverse landscape of software in different stages of parallelization exists at all times. Unfortunately, in this future, the inherent rigidity in current proposals for CMP designs (most notably number and size of cores) makes it hard to come up with a "universal" CMP that can accommodate this software diversity.

In this talk I will discuss Core Fusion, a CMP architecture where cores can "fuse" into larger cores on demand to execute sequential code very fast, while still retaining the ability to operate independently to run highly parallel code efficiently. Core Fusion builds upon a substrate of fundamentally independent cores and conventional memory coherence/consistency support, and enables the CMP to dynamically morph into different configurations to adapt to the changing needs of software at run-time. Core Fusion does not require a special ISA, it leverages mature micro-architecture technology, and it can interface with the application through small extensions encapsulated in ordinary parallelization libraries, macros, or directives.

In 2005, he and his students received the Best Paper Award at HPCA-11 for their work on checkpointed early load retirement. Earlier on, his work on speculative synchronization was featured in IEEE Micro's 2003 Top Picks from Microarchitecture Conferences as one of the "most industry relevant and significant papers of the year in computer architecture." Martínez is the recipient of a NSF CAREER Award and, more recently, an IBM Faculty Award.

His teaching responsibilities at Cornell include computer architecture at both undergraduate and graduate levels. He also organizes the AMD Computer Engineering Lecture Series.