Announcing the Final Examination of Mr. Heng Tan for the degree of Doctor of Philosophy in Electrical Engineering

Date: Monday, Nov 5, 2007
Time: 3:00 p.m.
Room: HC 202
Dissertation title: A Multi-Layer FPGA Framework Supporting Autonomous
Runtime Partial Reconfiguration

Partial reconfiguration is a unique capability provided by several Field Programmable Gate Array (FPGA) vendors recently, which involves altering part of the programmed design within an SRAM-based FPGA at run-time.  In this dissertation, a Multilayer Runtime Reconfiguration Architecture (MRRA) is developed, evaluated, and refined for Autonomous Runtime Partial Reconfiguration of FPGA devices. Under the proposed MRRA paradigm, FPGA configurations can be manipulated at runtime using on-chip resources. Operations are partitioned into Logic, Translation, and Reconfiguration layers along with a standardized set of Application Programming Interfaces (APIs).  An MRRA mapping theory is developed to link the general logic function and area allocation information to the device related physical configuration level data by using mathematical data structure and physical constraints. A corresponding logic control flow is also developed to make the entire process autonomous.  Several prototype MRRA systems are developed on a Xilinx Virtex II Pro platform.  Area, speed and power optimization techniques are developed based on the developed Xilinx prototype. Evaluations and analysis of these prototype and techniques are performed on a number of benchmark and hashing algorithm case studies.  The results indicate that based on a variety of test benches, up to 70% reduction in the resource utilization, up to 50% improvement in power consumption, and up to 10 times increase in run-time performance are achieved using the developed architecture and approaches compared with the Xilinx baseline reconfiguration flow.  Finally, a Genetic Algorithm (GA) for a FPGA fault tolerance case study is evaluated as a ultimate high-level application running on this architecture. It demonstrated that this is a hardware and software infrastructure that enables an FPGA to dynamically reconfigure itself efficiently under the control of a soft microprocessor core that is instantiated within the FPGA fabric. Such a system contributes to the observed benefits of intelligent control, fast reconfiguration, and low overhead.

Major: Computer Engineering

Educational Career:
B.S., 2000, Dalian University of Technology
M.S., 2004, University of Central Florida

Committee in Charge:
Dr. R. F. DeMara
Dr. M. Chatterjee
Dr. H. Zhou
Dr. Z. Shen

Approved for distribution by Ronald F. DeMara, Committee Chair, on October 29, 2007.

The public is welcome to attend.