Department of Electrical Engineering & Computer Science
Department of Electrical Engineering & Computer Science

Deliang Fan


JOURNAL PUBLICATIONS
 
  1. [TCAD'17] S. Angizi, Z. He, N. Bagherzadeh and D. Fan, “Design and Evaluation of a Spintronic In-Memory Processing Platform for Non-Volatile Data Encryption,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017 (accepted)
  2. [TMAG'17] S. Pyle, D. Fan, R. DeMara, “Compact Spintronic Muller C-Element with Near-Zero Standby Energy,” IEEE Transactions on Magnetics, 2017 (accepted)
  3. [MAGL'17] Z. He, S. Angizi, and D. Fan, “Current Induced Dynamics of Multiple Skyrmions with Domain Wall Pair and Skyrmion-based Majority gate Design,” IEEE Magnetics Letters, vol.8, March 30, 2017 [pdf]
  4. [TCAD'17] A. Roohi, R. Zand, D. Fan and R. DeMara, “Voltage-based Concatenatable Full Adder using Spin Hall Effect Switching,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2017 (accepted, in press) [pdf]
  5. [JETC'17] K. Yogendra, C. Liyanagedera, D. Fan, Y. Shim and K. Roy, “Coupled Spin-Torque Nano-Oscillator based Computation: A Simulation Study,” ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no.4, July 2017 [pdf]
  6. [TETC'17] Z. He and D. Fan, “Energy Efficient Reconfigurable Threshold Logic Circuit with Spintronic Devices,” IEEE Transactions on Emerging Topics in Computing, vol.5, no.2, May 2017 [pdf]
  7. [JETCAS'17] S. Salehi, D. Fan, R. DeMara, “Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 13, no. 3, May 2017 [pdf]
  8. [TNANO'17] R. Zand, A. Roohi, D. Fan and R. DeMara, “Energy-Efficient Nonvolatile Reconfigurable Logic using Spin Hall Effect-based Lookup Tables,” IEEE Transactions on Nanotechnology, vol. 16, no. 1, pp.32-43, Jan. 2017 [pdf]
  9. [TCAD'16] X. Fong, Y. Kim, K. Yogendra, D. Fan, A. Sengupta, and K. Roy, “Spin-Transfer Torque Devices: Prospects and Perspectives,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, no. 1, pp.1-22, Jan 2016, DOI: 10.1109/TCAD.2015.2481793 [pdf]
  10. [TED'16] K Yogendra, D. Fan, B. Jung and K. Roy, “Magnetic Pattern Recognition using Injection Locked Spin Torque Nano-Oscillators", IEEE Transactions on Electron Devices, vol. 63, no. 4, pp.1674-1680, Feb. 2016 [pdf]
  11. [TNANO'15] D. Fan, S. Maji, K. Yogendra, M. Sharad and K. Roy, “Injection Locked, Spin Hall Induced Coupled-Oscillators for Energy Efficient Associative Computing,” IEEE Transaction on Nanotechnology (TNANO), Vol. 14, No. 6, Aug, 2015. DOI: 10.1109/TNANO.2015.2471092 [pdf]
  12. [TNNLS'15] D. Fan, M. Sharad, A. Sengupta and K. Roy, “Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing,” IEEE Transaction on Neural Networks and Learning Systems (TNNLS), Aug. 2015. DOI: 10.1109/TNNLS.2015.2462731 [pdf]
  13. [TNANO'15] D. Fan, Y. Shim, A. Raghunathan and K. Roy, “STT-SNN: A Spin-Transfer-Torque Based Non-Linear Soft-Limiting Neuron for Low-Power Artificial Neural Networks,” IEEE Transactions on Nanotechnology (TNANO), June 2015. DOI: 10.1109/TNANO.2015.2437902 [pdf]
  14. [TMAG'15] K Yogendra, D. Fan and K. Roy, “Coupled Spin Torque Nano Oscillators for Low Power Neural Computation”, IEEE Transactions on Magnetics, Vol. 51, no. 10, June, 2015. DOI: 10.1109/TMAG.2015.2443042 [pdf]
  15. [TMAG'15] M. Sharad, D. Fan and K. Roy, “Energy-Efficient and Robust Associative Computing with Injection-Locked Dual Pillar Spin-Torque Oscillators”, IEEE Transactions on Magnetics, Vol. 51, No. 7, June 2015. DOI: 10.1109/TMAG.2015.2394379 [pdf]
  16. [JETCAS'15] K. Roy, D. Fan, X. Fong, Y. Kim, M. Sharad, S. Paul, S. Chatterjee, S. Bhunia, and S. Mukhopadhyay “Exploring Spin Transfer Torque Devices for Unconventional Computing”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Vol. 5, No. 1, March 2015. DOI: 10.1109/JETCAS.2015.2405171 [pdf]
  17. [TNANO'14] D. Fan, M. Sharad and K. Roy, “Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic,” IEEE Transaction on Nanotechnology (TNANO) Vol. 13, No. 3, May, 2014. DOI: 10.1109/TNANO.2014.2312177 [pdf]
  18. [TNANO'14] M. Sharad, D. Fan, and K. Roy, “Energy Efficient Non-Boolean Computing With Spin Neurons and Resistive Memory”, IEEE Transaction on Nanotechnology (TNANO), vol. 13, No.1, 2014. DOI: 10.1109/TNANO.2013.2286424 [pdf]
  19. [JAP'13] M. Sharad, D. Fan and K. Roy , “Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers”, Journal of Applied Physics (JAP), 114, 234906 (2013) http://dx.doi.org/10.1063/1.4838096 [pdf]


CONFERENCE PUBLICATIONS
 
  1. [ASPDAC'18] F. Parveen, Z. He, S. Angizi and D. Fan, “HieIM: Highly Flexible In-Memory Computing using STT MRAM,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 22-25, 2018, Jeju Island, Korea (accepted)
  2. [ASPDAC'18] S. Angizi, Z. He, F. Parveen and D. Fan, “IMCE: Energy-Efficient Bit-Wise In-Memory Convolution Engine for Deep Neural Network,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 22-25, 2018, Jeju Island, Korea (accepted)
  3. [ICCD'17] Z. He, S. Angizi and D. Fan, “Exploring STT-MRAM based In-Memory Computing Paradigm with Application of Image Edge Extraction,” IEEE International Conference on Computer Design (ICCD) , Nov. 5-8, 2017, Boston, MA (accepted)
  4. [ICCD'17] D. Fan and S. Angizi “Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM,” IEEE International Conference on Computer Design (ICCD) , Nov. 5-8, 2017, Boston, MA (accepted) [pdf]
  5. [NCAMA'17] S. Angizi and D. Fan , “IMC: Energy-Efficient In-Memory Convolver for Accelerating Binarized Deep Neural Network,” Neuromorphic Computing Symposium: Architectures, Models, and Applications , July 17-19, 2017, Knoxville, Tennessee
  6. [ICCAD'17] M. Yang, J. Hayes, D. Fan and W. Qian, “Design of Accurate Stochastic Number Generators with Noisy Emerging Devices for Stochastic Computing,” IEEE/ACM International Conference on Computer Aided Design, Nov 13-16, Irvin, CA (accepted)
  7. [ISLPED'17] F. Parveen, S. Angizi, Z. He and D. Fan , “Low Power In-Memory Computing based on Dual-Mode SOT-MRAM,” IEEE/ACM International Symposium on Low Power Electronics and Design, July 24-26, 2017, Taipei, Taiwan [pdf]
  8. [NANOARCH'17] Z. He, S. Angizi, F. Parveen and D. Fan , “High Performance and Energy-Efficient In-Memory Computing Architecture based on SOT-MRAM,” IEEE/ACM International Symposium on Nanoscale Architectures , July 25-26, 2017, Newport, USA
  9. [ISVLSI'17] D. Fan, S. Angizi and Z. He, “In-Memory Computing with Spintronic Devices,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany (invited) [pdf]
  10. [ISVLSI'17]S. Angizi, Z. He, F. Parveen and D. Fan, “RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany [pdf]
  11. [ISVLSI'17]F. Parveen, Z. He, S. Angizi and D. Fan, “Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany (Best Paper Award) [pdf]
  12. [MWSCAS'17]D. Fan, Z. He and S. Angizi, “Leveraging Spintronic Devices for Ultra-Low Power In-Memory Computing: Logic and Neural Network,” 60th IEEE International Midwest Symposium on Circuits and Systems, Aug. 6-9, 2017, Boston, MA, USA (invited)
  13. [ISCAS'17]F. Parveen, S. Angizi, Z. He and D. Fan, “Hybrid Polymorphic Logic Gate Using 6 Terminal Magnetic Domain Wall Motion Device,” IEEE International Symposium on Circuits & Systems (ISCAS), Baltimore, MD, USA, May 28-31, 2017 [pdf]
  14. [GLSVLSI'17]Z. He, S. Angizi, F. Parveen, and D. Fan, “Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-Memory Data Encryption”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017 [pdf]
  15. [GLSVLSI'17]S. Angizi, Z. He, and D. Fan, “Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017 [pdf]
  16. [GLSVLSI'17]Q. Alasad, J. Yuan, and D. Fan, “Leveraging All-Spin Logic to Improve Hardware Security”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017 [pdf]
  17. [DATE'17]Z. He, D. Fan, “A Tunable Magnetic Skyrmion Neuron Cluster for Energy Efficient Artificial Neural Network,” Design, Automation and Test in Europe (DATE), Lausanne, Switzerland, 27-31 March, 2017 [pdf]
  18. [ISQED'17]S. Angizi, Z. He, R. DeMara and D. Fan, “Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing,” 18th International Symposium on Quality Electronic Design(ISQED), Santa Clara, CA, USA, 13-15 March, 2017[pdf]
  19. [ISLPED'16]Z. He and D. Fan, “A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator”, International Symposium on Low Power Electronics and Design (ISLPED), San Francisco, CA, Aug. 8-10, 2016[pdf]
  20. [NANOARCH'16]D. Fan, “Low Power In-Memory Computing Platform with Four Terminal Magnetic Domain Wall Motion Devices”, IEEE/ ACM International Symposium on Nanoscale Architectures, , Beijing, China, July 18-20, 2016 [pdf]
  21. [GLSVLSI'16]D. Fan, “ Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate”, 26th GLSVLSI, Boston, Massachusetts, May 18-20, 2016[pdf]
  22. [IJCNN'16]C. Liyanagedera, K. Yogendra, K. Roy and D. Fan, “ Spin Torque Nano-Oscillator based Oscillatory Neural Network”, 2016 IEEE International Joint Conference on Neural Network (IJCNN), Vancouver, Canada, July 24-29, 2016[pdf]
  23. [ASPDAC'16]K. Yogendra, D. Fan, Y. Shim, M. Koo, and K. Roy, “ Computing with Coupled Spin Torque Nano Oscillators”, 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, Jan. 25-28, 2016[pdf]
  24. [ASPDAC'16]A. Sengupta, K. Yogendra, D. Fan and K. Roy, “Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses”, 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, Jan. 25-28, 2016[pdf]
  25. [DATE'14]K. Roy, M. Sharad, D. Fan and K. Yogendra, “Brain-inspired computing with spin torque devices”, Design, Automation & Test in Europe (DATE), 2014. (invited tutorial)[pdf]
  26. [ISVLSI'14]K. Roy, M. Sharad, D. Fan and K. Yogendra, “Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, July 9-11, 2014 (special session paper)[pdf]
  27. [DAC'13]M. Sharad, D. Fan, and K. Roy, “Ultra Low Power Associative Computing With Spin Neurons and Resistive Crossbar Memory,” IEEE/ACM Design Automation Conference (DAC), Austin, TX, June 2-6, 2013[pdf]
  28. [ISLPED'13]K. Roy, M. Sharad, D. Fan, and K. Yogendra, “Beyond Charge-Base Computing: Boolean and Non Boolean computing Using spin Devices,” International Symposium on Low Power and Design (ISLPED), 2013. (invited tutorial)[pdf]
  29. [ICCAD'13]K. Roy, M. Sharad, D. Fan, and K. Yogendra, “Exploring Boolean and Non Boolean Computing Using Spin torque Switches” International Conference on Computer-Aided Design (ICCAD), 2013. (invited tutorial)[pdf]
  30. [ISQED'13]M. Sharad, D. Fan, and K. Roy, “Low Power and Compact Mixed-Mode Signal Processing Hardware using Spin-Neurons,” IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, March 4-6, 2013[pdf]
  31. [E3S'13]M. Sharad, D. Fan, K. Yogendra, and K. Roy, “Ultra-Low Power Neuromorphic Computing with Spin-Torque Devices,” 3rd Berkeley Symposium on Energy Efficient Electronic Systems, 2013[pdf]


University of Central Florida