AREAS OF INTEREST
Ultra-Low Power In-Memory Computing based on Non-Volatile Memory
Over past decades, the amount of data that is required to be processed and analyzed by the computing systems has been increasing dramatically to exascale, which brings grand challenges for state-of-the-art computing system to simultaneously deliver energy efficient and high performance computing solutions. Such challenges mainly come from the well-known power wall (i.e. huge leakage power consumption limits the performance growth when technology scales down) and memory wall (including long memory access latency, limited memory bandwidth, energy hungry data transfer and huge leakage power consumption for holding data in volatile memory). Therefore, there is a great need to leverage innovations from both device technology and architecture to build an energy efficient and high performance computing platform. In order to address the above challenges, in-memory computing within non-volatile memory (NVM) has been proposed as a promising solution to reduce massive power hungry data traffic between computing and memory units, leading to significant improvement of entire system performance and energy efficiency.
Brain Inspired (Neuromorphic) Computing
- Explore various Non-Volatile Memory (NVM) device modeling, including STT-MRAM, SOT-MRAM, domain wall memory, racetrack memory, skyrmion memory, memristor, ReRAM, etc.
- Explore dual-mode NVM circuit and architecture designs that could simultaneously work as non-volatile memory and in-memory computing to greatly reduce data communication and thus improve system performance
- Related publications : [J17:MAGL'17], [C25:ISLPED'17], [C24:NANOARCH'17], [C23:ISVLSI'17], [C22:ISVLSI'17], [C21:ISVLSI'17], [C20:MWSCAS'17], [C19:ISCAS'17], [C17:GLSVLSI'17], [C12:NANOARCH'16]
Human brains are vastly more energy efficient at interpreting the world visually or understanding speech than any CMOS based computer system of the same size. Artificial Neural Networks (ANN) can perform human-like cognitive computing, such as vision, classification, and inference. The fundamental computing units of ANN are the neurons that connect to each other and external stimuli through programmable connections called synapses. The basic operation of an artificial neuron is summing the N weighted inputs and passing the result through a transfer (activation) function. Such neuron transfer functions can be efficiently implemented using ultro-low power spin-transfer torquede devies. Compared with state-of-the-art CMOS neuron, spin based neuron can potentially achieve more than two orders of lower energy consumption. Our research in this area include:
Non-Volatile In-Memory Data Encryption
- Physical modeling of nanoscale emerging devices for potential neuron or synapse applications, such as spin-transfer torque devices and memristors.
- Exploration of various neuromorphic computing models using spin based neuron, such as Deep Learning Convolutional Neural Network, Spiking Neural Network, Hierarchical Temporal Memory, Oscillatory Neural Network, etc
- Cross-layer (device/ circuit/ architecture) co-design for implementing complex machine learning tasks, such as pattern/ speech recognition, semantic reasoning, robotic control and motion detection
- Related publications : [J15:JETC'17], [J11:TCAD'16], [J10:TED'16], [J9:TNANO'16], [J8:TNNLS'16], [J7:TNANO'15], [J6:TMAG'15], [J5:TMAG'15], [J4:JETCAS'15], [J2:TNANO'14], [J1:JAP'13], [C15:DATE'17], [C10:IJCNN'16], [C9:ASPDAC'16], [C8:ASPDAC'16], [C7:DATE'14], [C6:ISVLSI'14], [C5:DAC'13], [C4:ISLPED'13], [C3:ICCAD'13], [C2:ISQED'13], [C1:Berkeley E3S'13],
With the onset and growth of the Internet of Things (IoT), there is an inundation of data in today's world. Meanwhile, most of the data are sensitive, such as health-monitoring or bio-metric data. The demand of energy efficient and high performance cryptographic components is becoming much stronger nowadays and will keep growing rapidly in the future. With the great advancement of fabrication technology and commercialization progress, Magnetic Random Access Memory (MRAM) is becoming a next-generation universal non-volatile memory technology to greatly change the state-of-the-art memory hierarchy due to its non-volatility, zero leakage power in un-accessed bit-cell, less than fJ/bit memory write energy (close to SRAM), high integration density (2X more than SRAM), excellent endurance (~10 years) and compatibility with the CMOS fabrication process (back end of line).
We are exploring in-memory data encryption engine design by leveraging a novel dual mode MRAM design that could work simultaneously as non-volatile main memory and in-memory data encryption engine. The dual mode MRAM could (1) work as a non-volatile main memory with almost zero leakage power; (2) intrinsically implement bit-cell level complete set of in-memory logic functions (AND/NAND, OR/NOR, XOR/XNOR), which requires no add-on logic circuits to memory chip as in traditional designs. It thus results in almost zero area overhead and no sacrifice of memory capacity. Such intrinsic in-memory logic design could be then explored to develop in-memory data encryption engine that is capable of various algorithms, such as AES, PRESENT, SIMON, KATAN and etc. Compared with traditional data encryption engine, such in-memory data encryption engine could implement all of the computation within main memory, which eliminates massive data transfer between traditional memory and computing units, leading to much more energy efficient design. It is estimated that the energy consumption of such all in-memory data encryption engine could achieve at least one order lower energy consumption compared with ASIC designs. Meanwhile, such design also reduces the dependency on other computing unites, thus reducing the risk of malware and data theft during data communication.
- Related publications : [C25:ISLPED'17], [C24:NANOARCH'17], [C23:ISVLSI'17], [C22:ISVLSI'17], [C20:MWSCAS'17], [C18:GLSVLSI'17]
Non-volatile spin-torque switches can be used in designing reconfigurable Boolean logic blocks, which can provide enhanced scalability and energy efficiency resulting from reduced leakage of the spin based memory elements.
- Related publications : [J16:TCAD'17], [J15:TETC'17], [J14:TNANO'17], [J12:TNANO'17], [J3:TNANO'14],[C21:ISVLSI'17], [C19:ISCAS'17], [C14:ISQED'17], [C11:GLSVLSI'16]