Lab 2 - Hardware Security Primitive - PUF Designs

Part 1 | Part 2 | Part 3


Part 1: Download Supportive Materials - BASYS2 250K Board

For Lab2 - PUF Designs, we will keep on using the BASYS2 250K FPGA board. Note that the original FPGA board used for the CSAW 2011 PUF competition is the Atlys Board equipped with Spartan-6 FPGA chip. Again, the UCF file needs adjusted as what we have done in lab 1.

Step 1. Install the Xilinx ISE (I assume that all of you have already installed the ISE on your computers).

Step 2. Download the supportive materials from HERE. Extract the zipped file to your working folder.

Step 3. In the extracted PUF folder, you will find the Puf Design.pdf file. Please read it first.

ALERT: In section 3 - FPGA Board Interface, please be aware that all notations are valid for Atlys board. For our BASYS2 board, you will reassign the interface. A sample UCF file is listed below:

NET "clk" LOC = B8;
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "rst" LOC = G12; #BTN0 # also the dump command
NET "rx" LOC = C13;
NET "tx" LOC = D12;
NET "led" LOC = M5; #LED0
NET "sw<1>" LOC = E2; #SW6
NET "puf_en" LOC = C11; #BTN1
NET "sw<0>" LOC = N3; #SW7
NET "switch<0>" LOC = P11; #SW0
NET "switch<1>" LOC = L3; #SW1
NET "switch<2>" LOC = K3; #SW2

ALERT: In the section 6 - Appendix, it only shows you an example to generate one-port RAM. You need to generate two RAM files named "ram2kx8" and "ram1kx8". Both of Write Width 8, but the Write Depth are 2048 and 1024, respectively.

Step 4. In "VHDL Codes" folder, you can find all supportive hardware code for communication between your computer and your FPGA boards. You can create a project and include all the source files in the folder. Besides the ram2kx8 and ram1kx8 modules, the only module missing is the puf (the puf2 is same as the puf) which you need to design yourself.

Step 5. In the "Programs" folder, a terminal.exe program is available for the RS232 communication. You can use this one or the one Brandon recommended (XCTU software). Jeff also recommends a RS232 terminal for sending binary file from the computer to the FPGA board http://realterm.sourceforge.net/.

Step 6. Since we can only read and write binary data to/from RAM, we have to reply on the Python code "bin2txt.py" and "txt2bin.py" to help us conver ascii code and binary data. Please download the Python from http://www.python.org/download/releases/. Try to use the Python version lower than 2.7.5.

 

Part 1: Download Supportive Materials - BASYS3 FPGA Board

For Lab2 - PUF Designs, we may use the BASYS3 FPGA board. Note that the original FPGA board used for the CSAW 2011 PUF competition is the Atlys Board equipped with Spartan-6 FPGA chip. Again, the UCF file needs adjusted as what we have done in lab 1.

Step 1. Install the Xilinx Vivado (I assume that all of you have already installed the Vivado on your computers).

Step 2. Download the supportive materials from HERE. Extract the zipped file to your working folder.

Step 3. In the extracted PUF folder, you will find the Puf Design.pdf file. Please read it first.

ALERT: In section 3 - FPGA Board Interface, please be aware that all notations are valid for Atlys board. For our BASYS3 board, you will reassign the interface. A sample XDC file is listed below:

## Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]

set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

## Switches
set_property PACKAGE_PIN V17 [get_ports {switch[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {switch[0]}]
set_property PACKAGE_PIN V16 [get_ports {switch[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {switch[1]}]
set_property PACKAGE_PIN W16 [get_ports {switch[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {switch[2]}]
set_property PACKAGE_PIN W14 [get_ports {sw[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN W13 [get_ports {sw[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]

## LEDs
set_property PACKAGE_PIN U16 [get_ports {led}]
set_property IOSTANDARD LVCMOS33 [get_ports {led}]

##Buttons
set_property PACKAGE_PIN W19 [get_ports puf_en]

set_property IOSTANDARD LVCMOS33 [get_ports puf_en]
set_property PACKAGE_PIN U18 [get_ports rst]

set_property IOSTANDARD LVCMOS33 [get_ports rst]

#USB-RS232 Interface
set_property PACKAGE_PIN B18 [get_ports rx]

set_property IOSTANDARD LVCMOS33 [get_ports rx]
set_property PACKAGE_PIN A18 [get_ports tx]

set_property IOSTANDARD LVCMOS33 [get_ports tx]

ALERT: In the section 6 - Appendix, it only shows you an example to generate one-port RAM. You need to generate two RAM files named "ram2kx8" and "ram1kx8". Both of Write Width 8, but the Write Depth are 2048 and 1024, respectively.

In Vivado, you can generate the Block RAM IP cores by first opening the IP catalog (Window -> IP Catalog) and selecting the Block RAM item from the catalog (Memories & Storage Elements -> RAMs & ROMs -> Block Memory Generator). Set the Write Width to 8 and Write Depth to 2048 for "ram2kx8", and 8 and 1024 for "ram1kx8", and enabled in both cases to "Always Enabled". No other settings need to be changed.

Step 4. In "VHDL Codes" folder, you can find all supportive hardware code for communication between your computer and your FPGA boards. You can create a project and include all the source files in the folder. Besides the ram2kx8 and ram1kx8 modules, the only module missing is the puf (the puf2 is same as the puf) which you need to design yourself.

Step 5. In the "Programs" folder, a terminal.exe program is available for the RS232 communication. You can use this one or the one Brandon recommended (XCTU software). Jeff also recommends a RS232 terminal for sending binary file from the computer to the FPGA board http://realterm.sourceforge.net/.

Step 6. Since we can only read and write binary data to/from RAM, we have to reply on the Python code "bin2txt.py" and "txt2bin.py" to help us conver ascii code and binary data. Please download the Python from http://www.python.org/download/releases/. Try to use the Python version lower than 2.7.5.

Enjoy!