Lab 3 - Vulnerabilities of Computing Platforms

Part 1 | Part 2 | Part 3


In this lab, you will be provided the source VHDL code of a full 8051 microprocessor and related software/hardware code to implement the 8051 microprocessor to FPGA boards. Similar to Lab 1, you are free to explore all the vulnerabilities of the microprocessor and insert hardware Trojan designs which can later be used by malicious software code to cause erroenous results to the computing platform.

Note: The purpose of hardware Trojan designs on computing platform is different from that of ASIC design. Here you should put both software and hardware into consideration other than letting the hardware Trojans do malicious work alone.

Part 1: Download Supportive Materials

Note: If you are using Basys 3 board, a detailed tutorial is presented at Lab3-Tutorial.

The source code is provided as part of the 2011 NYU-Poly CSAW competition so the guideline (8051_Guide.pdf) is also written for the competition. With some corrections, the guideline can be used for our lab. The related 8051 VHDL code and supporting software programs are avaialble here: 8051_programs.zip, 8051Core.zip.

Corrections/Modifications of the 8051_Guide.pdf:

  1. If we use Basys2-250 FPGA board other than the Atlys FPGA, the UCF file should be updated. The new UCF file can be downloaded HERE.

    If we use Basys3 FPGA board other than the Atlys FPGA, a new xdc file will be used (in Xilinx Vivado, xdc file is used instead of UCF file in Xilinx ISE). The new xdc file can be downloaded HERE.

  2. Switches and buttons: according to the new UCF file, 'BTNC' in the guide is replaced by 'BTN0', 'BTNU' is relaced by 'BTN1'.

  3. Memory generation: even though the guide asks you to generate 1KB memory for the 'ramx1kx8' module, you should actually generate a 4KB (width: 8, depth: 4096) in order to make sure the 8051 core works correctly. Note that the UART port will only read/write to the first one KB of the 4KB memory.

  4. DCM generation: Figure 21 is incorrect for Basys2 board because the Spartan 3E FPGA does not support 'Clocking Wizard'. Instead, we will generate a DCM_SP module with details in DCM_SP generation steps showed below.

  5. Because we use a DCM_SP module to generate low frequency clock signal, the top module should be updated accordingly. The new top module can be downloaded HERE to replace the old 'mc8051_fpga.vhd' file.

  6. Clock signal frequency: Similar to our Lab 2 - PUF, we need to adjust the clock frequency from 100MHz to 50MHz to make sure the UART port work at 9600 Baud rate. In 'inc.h' file,
    // The xtal-osc clock freq
    //
    //parameter XTAL_CLK = 100000000;
    parameter XTAL_CLK = 50000000;

  7. To help you test your design, a sample binary file (HELLO.bin) can be downloaded.

DCM_SP generation:

Enjoy!