Taping Out Your Chip

EEE5390

1. Pads and padframe

A TA session will be held to discuss the pads and pad frame (after we have a TA for the course).

The pads can be found in the following library:

/home/jinyier/cdscad6/VLSI_PAD_FRAME

Please first copy the whole PAD folder to your own cdscad6/ directory using the command:

cp -r /home/jinyier/cdscad6/VLSI_PAD_FRAME ~/cdscad6/

To access this library from your Library Manager add the following line to your cds.lib file:

DEFINE VLSI_PAD_FRAME ~/cdscad6/VLSI_PAD_FRAME

The library contains PadInDigital, PadOutDigital, padVdd, padVss, as well as padInOut_analog for analog terminals. These cells contain symbols and layout that you can use, and also schematics that you can look at to see what is inside each pad. Before insert the pads into your layout, please run the functional testing of all pads you are about to use and make sure they are functioning (and make sure that you know how to connect your design to the pads). NOTE: Please spend sometime to understand the structure of each pads and their connectors. For example, the PadInDigital is used to link external signals into internal signals, such as the reset, clk, etc. Please make sure the direction of each pad before you add them into your design.

An example pad frame you can use by copying into your own library is the cell "PAD_FRAME" in the "VLSI_PAD_FRAME" library. You can then change the individual pads if needed to be the appropriate input/output for your core, and don't forget to be sure to include power and ground (if you remove the supplied power and ground pads.)

 

2. Generate the GDS file (IC6)

For students who are using IC5, the interface may be slightly different so please serach online for details.

In the Command Interpreter Window (CIW) chose File->Export->Stream.

streamout

In the 'Stream File*' item, please type in the output file name using the format of 'filename.gds' or 'filename.gds2'.

Select the 'NCSU_TechLib_ami06' for the Technology Library.

Then choose the library folder where your design locates.

Since you will have more than one design in the selected folder, please select the final design (the top level design) in the Toplevel Cell(s) item. Choose the 'layout' for the View.

Then click the Options, an StreamOut Option window would open, similar to the following (after selecting the Layers card):

streamout layers

Here, click the 'Load File' button to specify the layermapping file from "~/ncsu-cdk-1.6.0.beta/pipo/streamOutLayermap". Click Ok. All layers will be loaded, press OK. Back to the Stream Out window, click Translate. A report file will pop out showing the translation process. If no error occurs, a GDS file will be generated under your cdscad6 folder.

If you cannot find streamOutLayermap in your pipo folder, please run the following command to copy that file to your own folder:

cp /home/jinyier/ncsu-cdk-1.6.0.beta/pipo/streamOutLayermap ~/ncsu-cdk-1.6.0.beta/pipo/

 

3. Check the generated GDS file

After you generate the GDS file, you need to double check whether the GDS file is correctly generated. To do this, please first create an empty library under the AMI06 process.

In the Command Interpreter Window (CIW) chose File->Import->Stream.

streamin

Similar to the Stream Out window, please specify the Stream File* as the one just generated. The 'Destination Library*' will be the empty library you generated for testing purpose. You also need to specify the 'Top Cell' module.

Then click the Options, an StreamIn-Option window would open. Again, select the Layers card and click the 'Load File' button to specify the layermapping file from "~/ncsu-cdk-1.6.0.beta/pipo/streamInLayermap". Click Ok. All layers will be loaded, press OK. Back to the Stream In window, click Translate.

Please run simulation on the streamIn layout to make sure the simulation results are exactly the same as those in the original layout. Note that since the streamIn layout does not contain any pin information, you need to add pins again before getting the extracted version for simulation.

 

4. Submitting your design to MOSIS (Using MOSIS MEP account).

This is a two-step procedure: "Create New Project" form must be completed first, followed by a "Fabricate Form".

MOSIS New Project Request

Go to www.mosis.com -> Log In (Account Management) -> Create New Project. Fill in and submit this form. Some of the fields are explained below.

"Account Number" and "Account Password" should be requested from the instructor.

Save your design password and design number generated after submission, as it will be required for further steps!

Run Type: Shared IC Fabrication Run

Design Rules: Scalable CMOS

Technology: SCN3M_SUBM (if the second layer of poly is not used); SCN3ME_SUBM (if the second layer of poly is used).

Design Name and Password (pick one for your project)

Export Control: Standard

Substrate: none

Run Date Requested: Pick the most recent date

Needs Library Installation: No

IP Included: none

Fill Authorized: Yes

Foundry: On Semi

Intended Disposition: Research

Design Size X and Y: should include the entire chip with pads

Pad Count: How many pads used in the design (including signals pads and power pads)

Quantity Packaged: 5

Package Name: DIP40 or DIP28 depending on the number of pads in your design

Rotation in Package: None

Bonding Diagram Supplier: MOSIS

Downbond Locations: None

Quantity Unpackaged: 0

You can leave Optional Parameters blank

 

Fabricate Form

After you submit the new design request, you would get confirmation email with project number. Go to Log In page again, use the project number and password under the Project Management column.

Go to Project Request -> Fabricate

Layout Transfer Method: I will upload layout via secure web form (HTTPS)

Compression/Encryption: Uncompressed

Next, you need to generate the Checksum and Count for you GDS file. MOSIS provides a program (mosiscrc.exe) (Check https://www.mosis.com/pages/support/submit/term_chksum for more details. Download the mosiscrc.exe and run "mosiscrc.exe -b yourdesign.gds" )

Layout Status: Final

Layout Format: GDS

Top Structure: the name of yout layout cell

After you submit the fabrication form, a link will be provided to upload your layout file. Click the link and upload the GDS file. With this done, you should receive an email stating that your design has passed the manufacturability review and is queued for fabrication (in case of DRC errors, the email will tell you the errors of the layout which you should fix before you resubmit the layout file).