Research Interests

Image Signal Processing	VLSI Chip Design
Video Coding Applications and Their Implementations	Reconfigurable Computing for Signal Processing Applications

PUBLICATIONS

- S. Kodipyaka and J. Lee, “H.264/AVC Motion Estimation Architecture with Adaptive Search Range Using Partial Reconfiguration”, Submitted to Special Issue on Configurable Computing: Configuring Algorithms, Processes, and Architecture (CAPA), ACM Transactions on Embedded Computing Systems (TECS).
- J. Huang and J. Lee, “A Self-Reconfigurable Platform for Scalable DCT Computation using Compressed Partial Bitstreams and BlockRAM Prefetching”, To appear in Special Issue on Algorithm/Architecture Co-Exploration of Visual Computing, IEEE Transactions on Circuits and Systems for Video Technology (TCSVT).
- J. Huang, S. Kodipyaka, and J. Lee, Submitted to Special Issue on Embedded Systems for Real-time Multimedia, ACM Transactions on Embedded Computing Systems (TECS).
- J. Huang and J. Lee, “Efficient VLSI Architecture for Video Transcoding”, To appear in IEEE Transactions on Consumer Electronics (TCE).
- S. Kodipyaka and J. Lee, “A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial Reconfiguration”, In the Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp. 219-225, Las Vegas, Nevada, July 13-16, 2009.
- J. Huang and J. Lee, “A Self-Reconfigurable Platform for Scalable DCT Computation using Compressed Partial Bitstreams and BlockRAM Prefetching”, In the Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 67-72, Tampa, Florida, May 13-15, 2009. (Regular paper - 24% acceptance rate)
- J. Huang, M. Parris, J. Lee, and R. F. DeMara, “Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration”, To appear in Special Issue on Configurable Computing: Configuring Algorithms, Processes, and Architecture (CAPA), ACM Transactions on Embedded Computing Systems (TECS).
- Y. Liu, S. Santhanam, and J. Lee, “Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study”, In the Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, U.S.A., July 14-17, 2008.
- J. Huang, M. Parris, J. Lee, and R. F. DeMara, “Scalable FPGA Architecture for DCT Computation using Dynamic Partial Reconfiguration”, In the Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, U.S.A., July 14-17, 2008.
- J. Huang, H. Li, and J. Lee, “A Fast FPGA Implementation of Tate Pairing in Cryptography over Binary Field”, In the Proceedings of International Conference on Security and Management (SAM), Las Vegas, U.S.A., July 14-17, 2008.
- J. Huang, J. Lee, and Y. Ge, “An Array-based Scalable Architecture for DCT Computations in Video Coding”, In the Proceedings of IEEE International Conference on Neural Networks and Signal Processing, Zhenjiang, China, June 7-11, 2008. (Best Student Paper Award)
- J. Huang and J. Lee, “Unified Architecture for Video Coding”, In the Proceedings of IEEE Symposium on Low-Power and High-Speed Chips, Yokohama, Japan, April, 2008.
- Y. Liu and J. Lee, “A High Throughput FPGA Architecture for DBP Application”, In the Proceedings of IEEE Symposium on Low-Power and High-Speed Chips, Yokohama, Japan, April, 2008.
- M. Kang, J. Lee, and C. Ryu, “Half-Pixel Motion Estimation Using Recursion Equation in Frequency Domain”, In the Proceedings of the 22nd International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), Pusan, Korea, July, 2007.
- J. Lee, “Memory Efficient Multi-Resolution Motion Estimation in the Transform Domain”, In the Proceedings of the 22nd International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), Pusan, Korea, July, 2007.
- J. Lee, C. Ryu, and M. Kang, “Half-Pixel Motion Estimation and Compensation Algorithm in DCT-based Transform Domain Using Recursion Equation”, In the Proceedings of the Joint Conference on Communications & Information (JCCI), Pyeongchang, Korea, May, 2007.
- J. Lee and C. Ryu, “A Wavefront Array Processor Utilizing a Recursion Equation for ME/MC in the Frequency Domain”, The Journal of KICS, Vol. 31, No. 10C, pp. 1000-1010, Oct. 2006.
- J. Lee, N. Vijaykrishnan, M. J. Irwin, and R. Chandramouli, “Block-based Frequency Scalable Technique for Efficient Hierarchical Coding”, IEEE Transactions on Signal Processing, Vol. 54, pp. 2559-2566, Jul. 2006.
- J. Lee, N. Vijaykrishnan, and M. J. Irwin, “Inverse Discrete Cosine Transform Architecture Exploiting Sparseness and Symmetry Properties”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, pp. 655-662, May 2006.
- J. Lee, N. Vijaykrishnan, M. J. Irwin, and W. Wolf, “An Efficient Architecture for Motion Estimation and Compensation in the Transform Domain”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, pp. 191-201, Feb. 2006.
- H. Cho and J. Lee, “Terminal and method for transporting still picture”, Patent (No.: US6956971), Oct. 18, 2005.
- J. Lee, N. Vijaykrishnan, and M. J. Irwin, “High Performance Array Processor for Video Decoding”, In the Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 28-33, Florida, U.S.A., May, 2005.
- J. Lee, N. Vijaykrishnan, M. J. Irwin, and R. Radhakrishnan, “Inverse Discrete Cosine Transform Architecture Exploiting Sparseness and Symmetry Properties”, In the Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), Texas, U.S.A., Oct., 2004.
- J. Lee, “Device for generating memory address and mobile station using the address for writing/reading data”, Patent (No.: US6788617), Sept. 7, 2004.
- J. Lee, N. Vijaykrishnan, and M. J. Irwin, “Efficient VLSI Implementation of Inverse Discrete Cosine Transform”, In the Proceedings of International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Montreal, Canada, May, 2004.
- J. Lee, N. Vijaykrishnan, M. J. Irwin, and W. Wolf, “An Architecture for Motion Estimation in the Transform Domain”, In the Proceedings of International Conference on VLSI Design, Mumbai, India, Jan., 2004.
- J. Lee, N. Vijaykrishnan, M. J. Irwin, and R. Chandramouli, “An Efficient Implementation of Hierarchical Image Coding”, In the Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), Seoul, Korea, August, 2003.
- J. Lee, “Pipelined discrete cosine transform apparatus”, Patent (No.: US6577772), Jun. 10, 2003.
- J. Lee, “Vorrichtung zum Erzeugen einer Speicheradresse, Mobilstation, die diese Vorrichtung verwendet, und Verfahren zum Schreiben/Lesen von Daten”, Patent (No.: DE10036446A1), Mar. 1, 2001.
- H. Cho and J. Lee, “Terminal und Verfahren zum Transportieren von Standbildern”, Patent (No.: DE10035109A1), Feb. 8, 2001.
- J. Park, J. Lee, B. Choi, and J. Jeong, “Frequency Domain Deblocking in DCT-Based Image Compression”, In the Proceedings of International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), pp. 67-72, 1998.
- J. Park, J. Lee, S. Kim, B. Choi, and J. Jeong, “A Novel Deblocking Method in DCT-Based Image Coding”, In the Proceedings of IEEE International Workshop on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 706-709, 1998.
- J. Lee, M. Kim, and J. Jeong, “Blocking Artifacts Reduction for Improving Visual Quality of Highly Compressed Images”, The Journal of KICS, Vol. 22, No. 8, Aug. 1997.