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EEL4768
Computer Architecture Section 2 Location/Time: Lectures: Section 2 HEC 0102, (TuTh) 04:30pm to 05:45 pm.
Labs:HEC338,
Sections
0011(Mo) 9:00am-11:50am,
0012(Tu)
12:00pm-2:50pm,
0013 (We) 9:00am-11:50am,
0014 (Th) 12:00pm-2:50pm,
0015 (Fr) 9:00am-11:50am,
0016 (Fr) 12:00pm-2:50pm. Instructor:
Dr. Jun
Wang, HEC 320, 823-0449 (office), juwang@mail.ucf.edu.
office hours (TuTh) 3:15pm-4:15pm.
TAs(tentative):
LABs 0011-12 Rizwan
Ashraf
rizwan_a_ashraf@hotmail.com 0013-14 Yu Bai
yubai.2003@gmail.com 0015-16
Christopher Mitchell
Mitchell@cs.ucf.edu HW Grading Naveed Imran
Email:
naveed@knights.ucf.edu office hours
are Tuesday and Thursday 2pm-3pm. Course pages:
http://www.eecs.ucf.edu/~jwang/Teaching/EEL4768-f11
WebCourses@UCF: everything Course Materials
All course documents including lecture slides, lecture notes, homework
assignments and solutions, and other helpful course resources will be
uploaded on WebCourses@UCF via MyUCF portal. Your up-to-date grades will be uploaded
on Grade Book in WebCourses@UCF. Please check
upgrades regularly. The
discussion forum in WebCourse@UCF will
create several discussion forums available for students, TA and faculty
to share information. You can use it to ask questions, answer questions
and share design, implementation, simulation and debug ideas and
experience. Textbook (Required) Computer Architecture: A
quantitative approach, 4th edition, by Patterson & Hennessy (References) Computer Organization
and Design, revised 3rd edition, by Patterson & Hennessy
HDL Programming
Fundamentals VHDL and Verilog, by Nazeib M. Botros Other Handouts, book chapters,
articles, conference papers and URLs will supplement course material. Course Description
Computer system performance and evaluation, Control and datapath design, Arithmetic Logic Unit, microprogrammed architectures, instruction and
arithmetic pipelines, cache and virtual memory, and RISC vs. CISC.
Students will also practice first-hand design and implementation of a
RISC pipeline microprocessor and an application system. Prerequisites
EEL3801/CDA3103 Computer Organization plus COP3402 System Software for CS
majors Course Assessment Outcomes This course is designed for advanced
undergraduate computer engineering and computer science students. 1. The students shall be able to
understand register-transfer-level (RTL) design of control and data path,
and use software tools such as Xilinx ISE to simulate hardware designs
captured using hardware description language Verilog. 2. The students shall be able to
analyze the computer performance such as CPU execution time and average
memory access time. 3. The students shall understand the
fundamental concepts and techniques in computer architecture, including
instruction set architecture, pipelining, memory hierarchy and
exploitation of instruction-level parallelism. 4. The students shall be able to work
in teams to accomplish a project for design and implementation of a RISC
pipeline microprocessor and an application system. 5. The students shall be able to
write technical high level design and detailed design. Topics Computer System Performance and
Evaluation Hardware Description Language
(Verilog) Data Path and Control Level of Design
Instruction Set Principles and
Examples I/O (if time permitted) Grading Policy 1. Two equally weighted exams
(midterm and final) will be given during the course. 2. Four Lab assignments will be given
during the course and start from the third week. 3. 4-5 homework assignments will be
given during the course. 4. Final Grade will be calculated
according to the weight associated with each component listed:
Homework:
20%;
Midterm
Exam:
25%;
Final Exam:
25%;
Laboratory:
30% (5%, 5%, 8%, 12%). Grading Scale:
A >= 90; 80 =< B < 90; 70 =< C < 80; 60
=< D < 70; F < 60 Laboratory Schedule 1. Lab will begin in the third week. 2. The laboratory component is
structured as an open lab in ENGR257. The lab is using XUP Virtex-II Pro FPGA Evaluation Board as a hardware
platform. The Xilinx ISE 9.2i and ModelSim
software will be used as the software development environment.
Windows/UNIX/Linux environment simulation, application-level and assembly
programming environment are also prepared. 3. Topics:
Lab 1: Combinational Logic Design (e.g, an
8-bit adder/subtractor, a 4-to-1 MUX and 2-to-4
decoder)
Lab 2: Sequential Logic Design (e.g, a 4-bit
counter, and a finite state machine)
Lab 3: Decimal Push Button Counter (e.g, a
decimal counter stored in ROM and clocked by push button)
Lab 4: Team Project-Building a RISC Pipeline Processor and its
application system 4. Students are encouraged to play
with Xilinx ISE in own computers. 5. Lab TA will be in the lab at lab
section times, demonstrate Schematic Design/Verilog programming,
debugging and board hacking. He/she will assist in the interpretation of
results. The laboratory exercises will be presented in class and
performance will be evaluated by completion and reporting. Homework
Homework will be assigned in the format of problem solving, and assigned
reading. All homework must be completed on time. Special Needs
We try our best to accommodate any student with a disability. Please
contact the instructor or University
disability service center as soon as possible if you need special
accommodations. |