Welcome to the EEL 5722C Course Home Page! This serves as the syllabus for the course.
Instructor: Mingjie Lin, Associate Professor (HEC-416), Department of Electrical and Computer Engineering, tel: 407-882-2298, email: email@example.com Office Hours : M/W 3:00pm-5:00pm
TA: Sayyed Jaffar Ali Raza <firstname.lastname@example.org>
Lab1,2,3: Mo, We, Fr 3:00PM - 5:50PM @ENG1 O257
Recent advances in VLSI technology have enabled a new class of application-specific computer architectures that take advantage of application-level parallelism. These reconfigurable computers can be quickly customized at the hardware level to perform exactly the computation required in hardware, overcoming the fixed hardware configurations found in many contemporary microprocessors.
EEL5722 focuses on the most popular reconfigurable computing platform--FPGA. Its main course components include FPGA architectures, design flow, technology mapping, placement, routing, reconfigurable computing applications, and evolvable hardware. The overall objective is to study FPGA's history and its technology evolution, investigate the state-of-the-art FPGA-based reconfigurable computing both from a hardware and software perspective, and explore potential research opportunities of FPGA computing. To this end, we first review in detail the basic building blocks of field-programmable gate arrays (FPGAs). Second, we focus on the architecture for existing multi-FPGA systems and on compilation techniques for mapping applications described in a hardware description language to reconfigurable hardware. Finally, specific contemporary reconfigurable computing systems are examined to identify existing system limitations and to highlight opportunities for research. (3 credits)
EEL 3342C (Introduction to Digital Circuits and Systems) is prerequisite for this class. Experience in computing architecture and organization may be helpful in understanding some of the course material but is not required.
Lab Assignments (40%), Mid-Term Exam (30%), Design Projects and Presentation (30%).Letter grades are based on the weighted average of the above components.
Consultation with fellow students is encouraged, especially on design issues. However, directly copying another student's work defeats the purpose of the assignments and is an honor code violation. All written assignments should be original work. Portions of written work that are taken word-for-word from other authors (students or researchers) will be assigned a failing grade and may result in a failing grade in the course.
On-campus students will be doing labs using CAD software on UNIX workstations and PCs.
Research papers and book chapters will be suggested reading for each class to help stimulate discussion. More Xilinx FPGA background information can be found on this page.
Lab Projects : There will be five lab assignments that involve the development and use of CAD tools for FPGA applications. Specifically,
Course Philosophy : My goal is for students to understand the FPGA technology in depth and become familiar with the state-of-the-art in reconfigurable computing. During the course open research problems in the field will be noted and students will have the opportunity to begin preliminary investigation of these issues through classroom projects.
Schedule (minor changes possible throughout the semester )
|Event||Fall 2014||Topics||Notes||Supplementary Reading|
|Lecture 1,2||Introduction (Objectives, Expectations, Logistics), FPGA's History and Future|
||Xilinx ISE Tutorial
||FPGA Architecture I: Overall concept and programming methods||Verilog Tutorial|
|Lecture 5||HDL: Verilog vs. VHDL
||LUT & Routing Architecture
|Lecture 7||Lgoic Optimization and Technology Mapping
|Lecture 8||Algorithms: Solving probelms with Strategy
|Lecture 9||Basic Placement Algorithm
|Lecture 10||Advanced Placement Algorithm
|Lecture 11||Basic Routing Algorithm|
|Lecture 12||Advanced Routing Algorithm I||Old mid-term exams Sample 1, Sample 2, Sample 3
|Lecture 13||Advanced Routing Algorithm II
||midterm solutions (I omitted some duplicated problems)
|Lecture 14||FPGA Modern Application and Its Potential
FPGA Modern Application: Logic Emulation
|Lecture 15||Midterm Review
||In class, one-hour, closed book.
Note: You need to submit a lab report to
TA for each lab you finished. The due day is listed in the following
table. The format is here.
|Event||Fall 2017||Topics||Assignments||Pre-Study Suggestions||Pre-study + Supplementary Readings|
|Lab 1||Design and implement a decimal push button counter||1. Download Xilinx ISE Webpack and
install on your own computer.
2. Following ISE Quick Start Tutorial and play with ISE.
3. Choose a simple HDL example (either in Verilog or VHDL), and try simulating its functionality by following ISE Simulator (ISim) In-depth Tutorial.
4. Read XUPV2P Documentation to get familiar with the device used in the lab.
|1. XUPV2P Documentation (link)
2. XUPV2P Reference Designs (link)
3. ISE WebPACK Design Software (link)
4. ISE Simulator (ISim) In-depth Tutorial (link)
5. ISE Quick Start Tutorial (link)
|Lab 2||Display color on a VGA monitor||Lab2 manual
|Lab 3||Input from a PS/2 keyboard||Lab3 manual|
|Lab 4||Display PS/2 keyboard input on a VGA monitor||Lab4 manual|
|Lab 5||Display an image on a VGA monitor||Lab5 manual|