EEL 5722C - Field-Programmable Gate Array (FPGA) Design

Welcome to the EEL 5722C Course Home Page! This serves as the syllabus for the course.

Instructor: Mingjie Lin, Associate Professor (HEC-416), Department of Electrical and Computer Engineering, tel: 407-882-2298, email: mingjie@eecs.ucf.edu Office Hours : M/W 3:00pm-5:00pm

TA: Sayyed Jaffar Ali Raza <jaffar@knights.ucf.edu>


Time and Locations: Lecture: M, W 1:30PM-2:45PM @ Eng1 O383

Lab1,2,3: Mo, We, Fr 3:00PM - 5:50PM @ENG1 O257


Course Description

    Recent advances in VLSI technology have enabled a new class of application-specific computer architectures that take advantage of application-level parallelism. These reconfigurable computers can be quickly customized at the hardware level to perform exactly the computation required in hardware, overcoming the fixed hardware configurations found in many contemporary microprocessors.

    EEL5722 focuses on the most popular reconfigurable computing platform--FPGA. Its main course components include FPGA architectures, design flow, technology mapping, placement, routing, reconfigurable computing applications, and evolvable hardware. The overall objective is to study FPGA's history and its technology evolution, investigate the state-of-the-art FPGA-based reconfigurable computing both from a hardware and software perspective, and explore potential research opportunities of FPGA computing. To this end, we first review in detail the basic building blocks of field-programmable gate arrays (FPGAs). Second, we focus on the architecture for existing multi-FPGA systems and on compilation techniques for mapping applications described in a hardware description language to reconfigurable hardware. Finally, specific contemporary reconfigurable computing systems are examined to identify existing system limitations and to highlight opportunities for research. (3 credits)

Prerequisites:

    EEL 3342C (Introduction to Digital Circuits and Systems) is prerequisite for this class. Experience in computing architecture and organization may be helpful in understanding some of the course material but is not required.

Grading: 

    Lab Assignments (40%), Mid-Term Exam (30%), Design Projects and Presentation (30%).

Letter grades are based on the weighted average of the above components.

100-90% A, 89-88% A-, 87-83% B+, 82-80% B, 79-77% B-, 76-73% C+, 72-70% C, 69-68% C-, 67-63% D+, 62-60% D, 59-56% D-, Below 55 F

Honesty Policy:

    Consultation with fellow students is encouraged, especially on design issues. However, directly copying another student's work defeats the purpose of the assignments and is an honor code violation. All written assignments should be original work. Portions of written work that are taken word-for-word from other authors (students or researchers) will be assigned a failing grade and may result in a failing grade in the course.

Computer Requirements:

    On-campus students will be doing labs using CAD software on UNIX workstations and PCs.

Course text:

Reference Material: 

    Research papers and book chapters will be suggested reading for each class to help stimulate discussion. More Xilinx FPGA background information can be found on this page.

Lab Projects : There will be five lab assignments that involve the development and use of CAD tools for FPGA applications. Specifically,

       * Final Design Project: To be determined

Course Philosophy : My goal is for students to understand the FPGA technology in depth and become familiar with the state-of-the-art in reconfigurable computing. During the course open research problems in the field will be noted and students will have the opportunity to begin preliminary investigation of these issues through classroom projects.


Schedule (minor changes possible throughout the semester )

Event Fall 2014 Topics Notes Supplementary Reading
Lecture 1,2
Introduction (Objectives, Expectations, Logistics), FPGA's History and Future pdf
Lecture 3

Xilinx ISE Tutorial
pdf
Lecture 4

FPGA Architecture I: Overall concept and programming methods pdf Verilog Tutorial
Lecture 5
HDL: Verilog vs. VHDL
pdf
Lecture 6

LUT & Routing Architecture
pdf
Lecture 7
Lgoic Optimization and Technology Mapping
pdf
Lecture 8
Algorithms: Solving probelms with Strategy

Lecture 9
Basic Placement Algorithm
pdf
Lecture 10
Advanced Placement Algorithm
pdf
Lecture 11
Basic Routing Algorithm pdf
Lecture 12
Advanced Routing Algorithm I pdf Old mid-term exams  Sample 1, Sample 2, Sample 3
Lecture 13
Advanced Routing Algorithm II
midterm solutions (I omitted some duplicated problems)
Lecture 14
FPGA Modern Application and Its Potential
FPGA Modern Application: Logic Emulation

pdf
pdf
pdf

Lecture 15
Midterm Review


Midterm Exam

In class, one-hour, closed book.





pdf, pdf

Final Project




FPGA application


pdf























































Lab Schedule

Note: You need to submit a lab report to TA for each lab you finished. The due day is listed in the following table. The format is here.

Event Fall 2017 Topics Assignments Pre-Study Suggestions Pre-study + Supplementary Readings
Lab 1
Design and implement a decimal push button counter pdf 1. Download Xilinx ISE Webpack and install on your own computer.
2. Following ISE Quick Start Tutorial and play with ISE.
3. Choose a simple HDL example (either in Verilog or VHDL), and try simulating its functionality by following ISE Simulator (ISim) In-depth Tutorial.
4. Read XUPV2P Documentation to get familiar with the device used in the lab.
1. XUPV2P Documentation (link)
2. XUPV2P Reference Designs (link)
3. ISE WebPACK Design Software (link)
4. ISE Simulator (ISim) In-depth Tutorial (link)
5. ISE Quick Start Tutorial (link)
Lab 2
Display color on a VGA monitor pdf
Lab2 manual
Lab 3
Input from a PS/2 keyboard pdf
Lab3 manual
Lab 4
Display PS/2 keyboard input on a VGA monitor pdf
Lab4 manual
Lab 5
Display an image on a VGA monitor pdf
Lab5 manual


Homeworks

HW1

HW2

Final Project

The final due day is Nov. 30th, 2016

Download all source code here
==========================
Three Milestones:

1. Descoing Control Flow: 

Source code: control.v

Read the code, complete the FSM portion,

2. Data Path:

Source code: datapath.v

Read the code, complete the combinational logic portion,

Due by Nov. 28th midnight.

3. Complete the overall project

Due by Nov. 30th midnight.

The grade of final project consists of three parts: 60% correctness of code implementation. 20% the qaulity of source code. 20% the quality of final report.

All source code submissions will be scanned by the anti-plagiarism software provided by UCF.

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