Professor: Yier Jin ( Spring 2013, Spring 2014, Spring 2015, Spring 2016
Professor: Rickard Ewetz ( Fall 2016



Our design projects will be fabricated using the AMI C5F/N Process. This is a 0.6um (lambda=0.3um) 2 poly, 3 metal process. We will use the SCMOS_SUBM rules. For details see The Mosis Website.


We will be using a tool suite from Cadence Design Systems called Front to Back Design Environment 5.1.41 and hereafter just referred to as "Cadence". The first thing to do is to get Cadence set-up on your account by following the Install Guide. Next you will want to learn the basics of Cadence by following the Cadence Tutorial.

Remote Access

The VLSI servers ( can be reached by PC or laptops using remote access. You need to use vpn if you are working outside the campus.
Please contact Denise Tjong at if your NID is not activiated for VLSI server (please mention the course number, your NID in your email).



IRSIM is a tool for simulating digital circuits. It is a "switch-level" simulator; that is, it treats transistors as ideal switches. Extracted capacitance and lumped resistance values are used to make the switch a little bit more realistic than the ideal, using the RC time constants to predict the relative timing of events. Next you will want to learn the basics of IRSIM by following the IRSIM Tutorial.


Taping Out Your Chip

When you finalize your chip design and have passed DRC and LVS, the most exciting moment comes - taping out your chip. The tutorial for taping-out your chip is available on the page Taping Out Your Chip.


Previous Projects

1. CRC-32 Checksum Circuit by Grant Hernandez.