Tentative Course Schedule (This may be updated without prior notice)
|
Week |
Day |
Topics |
|
Assignment |
|
1 |
8/23 |
Syllabus |
|
|
|
|
8/25 |
Verilog |
|
|
|
2 |
8/30 |
Verilog |
|
|
|
|
9/1 |
Testbench; Course Introduction |
Chapter 1 |
|
|
3 |
9/6 |
Technology trends, performance measurements |
Chapter 1 |
Lab1 starts on 9/5! |
|
|
9/8 |
Quantitative principles Homework #1 assigned due on 9/15 midnight |
|
|
|
4 |
9/13 |
Instruction Set Principles |
Appendix B |
|
|
|
9/15 |
Pipelining basic and concepts 1 |
Appendix B |
Lab1 rept due on 9/19 12AM! |
|
5 |
9/20 |
Data path and control |
Appendix A |
Lab2 starts on 9/19! |
|
|
9/22 |
Homework #2 assigned |
Appendix A |
|
|
6 |
9/27 |
Pipelining basic and concepts 2 |
Appendix A |
|
|
|
9/29 |
Wrapup and talk about midterm exam |
Appendix A |
|
|
7 |
10/4 |
Instruction level parallelism |
Appendix A |
Lab3 starts on 10/3! |
|
|
10/6 |
Midterm Exam |
|
|
|
8 |
10/11 |
Instruction level parallelism |
Chapter 2 |
|
|
|
10/13 |
Homework #3 assigned |
Chapter 2 |
withdrawal deadline Oct 15th |
|
9 |
10/18 |
Instruction level parallelism |
Chapter 2 |
Lab4 starts on 10/18! |
|
|
10/20 |
Instruction level parallelism |
Chapter 2 |
|
|
10 |
10/25 |
Homework #4 assigned |
Chapter 2 |
|
|
|
10/27 |
FAQ of Lab4 |
Withdrawal Deadline |
|
|
11 |
11/1 |
Instruction level parallelism |
Chapter 2 |
|
|
|
11/3 |
Memory hierarchy |
Chapter 5 |
|
|
12 |
11/8 |
Memory hierarchy |
Chapter 5 |
|
|
|
11/10 |
Memory hierarchy |
Chapter
5 |
|
|
13 |
11/15 |
Memory hierarchy |
Chapter 5 |
Start demoing
your lab4 project |
|
|
11/17 |
Homework #5 assigned due |
Chapter 5 |
|
|
14 |
11/22 |
Virtual memory |
Chapter 5 |
|
|
|
11/24 |
NO CLASS
Thanksgiving Day |
|
|
|
15 |
11/29 |
Virtual memory |
Chapter 5 |
Lab4 report is
due on November 29, midnight |
|
|
12/1 |
Wrap up of the whole course |
|
|
|
16 |
12/8 Tu 4:00pm to 6:50pm |
Final exam in HEC
102 |
|
|