EEL 4783: HDL in Digital System Design

Course:

Spring 2024. 3 credits.

Lectures: MW 12:00PM-1:15PM @ CB 307

            Instructor Office Hours: MWF 4-5PM @ HEC439A

Course Instructor:

Mingjie Lin

Office: HEC 439A, Telephone: 407-882-2298

Email: mingjie@eecs.ucf.edu, Home Page: http://www.eecs.ucf.edu/~mingjie

TA:  Sanjay Gandham (sanjaygandham@ucf.edu)

Course Description:

This course provides a systematic introduction to the topic of HDL programming for designing embedded digital system. It emphasizes the basic ideas, and the practical aspects of HDL programming with FPGA devices. In addition, this course presents techniques for modeling hardware components at different levels of abstraction and many concepts including the various forms of expressing computations, sequential and parallel implementations, control-flow and data-flow, control dependency and data dependency, latency and throughput as well as the architecture design space of hardware data paths, finite state machines. Specific topics include:

•     Basic concepts of HDL

• Veilog language and its usage.

• How to use  Verilog to design large-scale and complicated digital systems.

• Identifying performance bottlenecks in a given hardware architecture and optimize it by transformations on hardware components

• How to use logic simulation to analyze and verity a HDL design.

Prerequisites:

EEL 3342: Digital Logic Design

Minimally Required Skills:

Basic logic design and basic software programming skills.

Recommended Text:

“Advanced Digital Design with the Verilog HDL" (2nd Edition) Hardcover – January 31, 2010  by Michael D. Ciletti

Grading:

The distribution of weights for the exams, assignments, and projects is as follows:

Midterm Exam	30%
Final Exam	20%
Final Project	25%
Assignments	25%

Students are encouraged to participate in class.

Honor System Policy:

Consultation with fellow students is encouraged, especially on design issues. However, directly copying another student's work defeats the purpose of the assignments and is an honor code violation. All written assignments should be original work. Portions of written work that are taken word-for-word from other authors (students or researchers) will be assigned a failing grade and may result in a failing grade in the course

Schedule (minor changes possible throughout the semester )

Event	Topics	Notes	Assignments
HDL/Verilog Fundamentals
Lecture 1	Introduction (Objectives, Expectations, Logistics)	pdf
Lecture 2		pdf
Lecture 2+	Intro to VHDL	pdf
Lecture 3	Logic Design with Behavioral Models	pdf
Lecture 3+	Carry Lookahead Adder	pdf
Lecture 4	Logic Design with Behavioral Models (cont.)	pdf
Lecture 5	More Complex Behavioral Models	pdf
Lecture 6	More Examples	pdf
Emerging/Alternative HDL Languages
Lecture 8	Intro to SystemC (Part 1)	pdf
Lecture 9	Intro to SystemC (Part 2)	pdf
Lecture 10	Intro to SystemVerilog	pdf
Emerging HDL/Verilog Techniques
Lecture 11	High Level Synthesis	pdf
Lecture 12	Final Review	pdf
Lecture 15
Advanced HDL/Verilog Optimizations
Lecture 16	Coding for HLS	pdf
Lecture 17	Architecting for Speed	pdf
Lecture 18	Architecting for Area	pdf
Lecture 19	Architecting for Power	pdf
Lecture 20

Final Exam