Department of Electrical Engineering and Computer Science,
EEE 3342C: Digital Systems
Instructor:
Dr. Mingjie Lin
Eng1 O224
Tel: 407-882-2298
E-mail: mingjie@eecs.ucf.edu
Meeting Time and Place:
TTH, 2:00pm-3:50pm @ Eng1 O224
Office Hours: MWF, 1:00pm-3:00pm @ HEC429A
Catalog Description:
EEE 3342C Digital Systems: PR: MAC 2311 (Calculus and Analytic Geometry I), MAC 2312 (Calculus and Analytic Geometry II), PHY 2048C
(Physics for Engineers & Scientists I), PHY 2049C (Physics for Engineers & Scientists II) all with a C (2.0) or better grade
Combinational and sequential logic circuits including registers, arithmetic units, memories, finite state machines, and design with programmable logic
devices.
Textbook(s) and Reference(s):
Fundamentals of Logic Design, Sixth Edition by Charles H. Roth and Larry L. Kinney, Cengage Learning
Course Goals:
Upon successful completion of this course, students would
Understand number systems and perform arithmetic operations on binary, octal and hexadecimal numbers.
Implement Boolean algebra, Logic gates and K-map techniques.
Use synthesis and analysis techniques in the design of combinational logic circuits.
Analyze and design circuits using combinational logic.
Analyze and design sequential circuits using all types of flip flops.
Design finite state machines
Course topics:
3. Boolean
Algebra 2. (pdf)
4. Applications of Boolean Algebra (pdf)
5. Karnaugh-Maps (pdf)
6. Multi-Level Gate Circuits (pdf)
7. Multiplexers, Decoders and Programmable Logic Devices (pdf)
8. Latches and Flip-Flops (pdf)
9. Register and Counters (pdf)
10. Sequential Circuits (pdfle)
11. State Graphs and Tables (pdf)
12. Circuits for Arithmetic Operations (pdf)
Assignments
Lab
This course has a lab component. In the lab, you will learn how to describe a logic design circuit in a Hardware Description Language (HDL). HDL is
similar to programming but it is specifically for a logic circuit. We use the HDL language called Verilog to build circuits, test them by doing a
waveform analysis on inputs and outputs of the circuit, you will then be able to download your circuit to a computer board that we have and test it.
Attendance Policy
Attendance of all Labs is MANDATORY.
Attendance of all lectures is expected and encouraged.
If a student misses a lecture, he/she is responsible for its content.
Missing three lectures results in a 3% reduction of a student’s final grade.
Missing two labs results in a student’s final grade of “F”.
Use of WebCourses
The class uses WebCourses to provide you with the lecture notes and homework assignments.
If you need to email the instructor or TAs about a grade, please use Webcourses mail. The university requires that we use the secure WebCourses
mail to discuss grades.
Grading Policy:
|
Homework assignments and Quizzes |
20% |
|
Lab assignments and reports |
15% |
|
Exam1 |
20% |
|
Exam2 |
20% |
|
Final Exam |
25% |
Letter grades are based on the weighted average of the above components.
|
100-90% A |
87-83% B+ |
79-77% B- |
72-70% C |
67-63% D+ |
|
89-88% A- |
82-80% B |
76-73% C+ |
69-68% C- |
62-60% D |
|
59-56% D- |
Below 55 F |
|
|
|
Please note:
All homework assignments are due one week from the day they are assigned.
Homework will be assigned, collected, and selectively graded.
Incomplete homework assignments can be submitted for partial credit.
No credit will be given for late assignments.
No makeover exams and/or homework assignments.
Final Exam is Comprehensive.
Honor
System Policy:
Consultation with fellow students is encouraged, especially on design issues. However, directly copying another student's work defeats the purpose of the assignments and is an honor code violation. All written assignments should be original work. Portions of written work that are taken word-for-word from other authors (students or researchers) will be assigned a failing grade and may result in a failing grade in the course