FPGA 2015
Program with Slides
Sunday February 22
Designer’s Day
This year, FPGA’15 program contains a new
Stephen Neuendorffer, Xilinx, Inc.
Chair: Satwant Singh, Lattice Semiconductor Corp.
(60 min) Physical Design Space Exploration
Ephrem Wu, Inkeun Cho (Xilinx, Inc.)
(Pushing the boundaries of high speed FPGA design)
(20 min) Using
Joshua Monson, Brad Hutchings (Brigham Young University) (Improving
Chair: Zhiru Zhang, Cornell University
(60 min) High Level Design Methods for Floating Point FPGAs Deshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski (Altera, Inc.) (New Floating Point support in Altera FPGAs)
(20 min)
Myron King, Jamey Hicks, John Ankcorn (Quanta Research Cambridge) (Design tradeoffs in Processor/Accelerator Communication)
(20 min) InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters
Nachiket Kapre (Nanyang Technological University), Harnhua Ng, Kirvy Teo, Jaco Naude (Plunify, Inc.) (Automatically tune EDA tools to meet timing more quickly)
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Lunch (Marriott Hotel Ferrantes Bayview Room – 10th floor) |
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Session 3 (Ferrante Room, Monterey Conf. Center) |
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Chair: Patrick Lysaght, Xilinx, Inc. |
(60 min) Unlocking FPGAs Using
(Building complete FPGA systems with HLS)
(20 min) Enhancing Hardware Design Flows within MyHDL Keerthan Jaic, Melissa C. Smith (Clemson University) (Generating FPGA designs using Python Libraries)
(20 min) Rapid Prototyping of Wireless Physical Layer Modules Using Flexible Software/Hardware Design Flow
James Chacko, Cem Sahin, Douglas Pfiel, Nagarajan Kandasamy, Kapil Dandekar (Drexel University) (Practical techniques for designing and implementing Software Designed Radio (SDR) systems)
3:30
Chen Cheng, CEO, BEEcube, Inc.
The BEEcube
Abstract:
After running BEEcube Inc for the past 7 years, I
learned many lessons the hard way as an entrepreneur fresh out of
engineer school. Behind the glory of being the #9 fastest growing
private company in Silicon Valley in 2013, there were many untold
stories about our FPGA technology based startup company. A startup
company is where dreams start by smart people, and also where harsh
reality squashes them. This is not one of those “unicorn”
Presenter Bio:
Dr. Chen Chang is the Chief Executive Officer at
BEEcube Inc. Previously he served as Chief Technology Officer at
BEEcube where he led the development of the BEE3 product. Dr. Chang was
the Chief Architect of the Berkeley Emulation Engine (BEE) project at
the University of California in Berkeley, leading the design and
implementation of three generations of
7:00pm Conference Reception (Marriott Hotel Ferrantes Bayview Room)
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Monday February 23
8:00am Continental Breakfast & Registration (Steinbeck Lobby/Conf. Center)
8:40am Opening Remarks (Steinbeck Forum/Conf. Center)
Deming Chen and George A. Constantinides
9:00am Session 1:
Chair: Herman Schmit, Altera, Inc.
Long paper: 25 minutes. Short paper: 5 minutes
Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs (Best
Paper Candidate)
Evan Wegley, Qinhai Zhang (Lattice Semiconductor Corp.)
Alex Rodionov (University of Toronto), David Biancolin (University of California, Berkeley), Jonathan Rose (University of Toronto)
Eddie Hung, Joshua M. Levine, Edward Stott, George A. Constantinides, Wayne Luk (Imperial College London)
RapidSmith 2: A Framework for
Technology Mapping into General Programmable Cells (short)
Alan Mishchenko, Robert Brayton (University of California, Berkeley),
Wenyi Feng, Jonathan Greene (Microsemi Corp.)
10:25am Poster Session 1 (Colton Room/Conf. Center)
12 posters (please refer to the list below)
11:25am Session 2: Configuration and Processing (Steinbeck Forum)
Chair: Steve Trimberger, Xilinx, Inc.
EURECA:
Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware (short)
Stuart Byma, Naif Tarafdar, Talia Xu, Hadi Bannazadeh, Alberto
12:20pm Lunch (Marriott Hotel Ferrantes Bayview Room)
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2:00pm Session 3: Architecture 1 (Steinbeck Forum)
Chair: Jonathan Rose, University of Toronto
Take the Highway: Design for Embedded NoCs on FPGAs (Best Paper Candidate) Mohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz (University of Toronto)
Enhancements in UltraScale CLB Architecture
Shant Chandrakar, Dinesh Gaitonde, Trevor Bauer (Xilinx, Inc.)
Martin Langhammer, Bogdan Pasca (Altera European Technology Centre)
3:15pm Poster Session 2 (Colton Room)
12 posters (please refer to the list below)
4:15pm Session 4: Architecture 2: Memory Systems (Steinbeck Forum)
Chair: Carl Ebeling, Altera, Inc.
Superoptimized Memory Subsystems for Streaming Applications
Joseph G. Wingbermuehle, Ron K. Cytron, Roger D. Chamberlain (Washington University, St. Louis)
MATCHUP: Memory Abstractions for Heap Manipulating Programs
Felix Winterstein (European Space Agency), Kermin Fleming (Intel Corporation),
Samuel Bayliss, George Constantinides (Imperial College London)
Impact of Memory Architecture on FPGA Energy Consumption
Edin Kadric, David Lakata, André DeHon (University of Pennsylvania)
Design Space Exploration of L1 Data Caches for
5:35pm Break before Banquet
6:30pm Banquet & Panel (Marriott Hotel Ferrantes Bayview Room)
Panel: Building a Healthy FPGA Ecosystem
Moderator: John Lockwood,
Panelists: Michael Adler (Intel), Dan Mansur (Xilinx), Derek Chiou (Microsoft), Mike Strickland (Altera), Jason Cong (University of California, Los Angeles), Allen Cantle (Nallatech)
The focus of the panel will be on how developers and vendors can bring killer applications, tools, and programmable logic devices to the market to accelerate datacenters for cloud computing. Questions to be answered by the panelists include:
1.How large can the ecosystem for programmable logic become?
2.What are you doing to help grow the programmable logic ecosystem?
3.What do you ask of others to grow the programmable logic ecosystem?
4.What is your call to action for the attendees of the FPGA’15 conference?
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Tuesday February 24
8:20am Continental Breakfast & Registration (Steinbeck Lobby)
9:00am Session 5: Processors and Accelerators (Steinbeck Forum)
Chair: Zhiru Zhang, Cornell University
Optimizing
Chen Zhang (Peking University), Peng Li (University of California, Los Angeles), Guangyu Sun (Peking University & University of California, Los Angeles),
Yijin Guan (Peking University), Bingjun Xiao (University of California, Los Angeles), Jason Cong (University of California, Los Angeles & Peking University)
Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors Aaron Severance, Joe Edwards, Guy G.F. Lemieux (University of British Columbia)
On Data Forwarding in Deeply Pipelined Soft Processors
Hui Yan Cheah, Suhaib Fahmy, Nachiket Kapre (Nanyang Technological University)
10:15am Poster Session 3 (Colton Room)
11 posters (please refer to the list below)
11:15am Session 6:
Chair: Brad Hutchings, Brigham Young University
Mingxing Tan, Steve Dai, Udit Gupta, Zhiru Zhang (Cornell University)
Numerical Program Optimization for
Xitong Gao, George A. Constantinides (Imperial College London)
Shane Fleming, David Thomas, George Constantinides (Imperial College London), Dan Ghica (University of Birmingham)
12:15pm Lunch (Marriott Hotel Ferrantes Bayview Room)
2:00pm Session 7: Circuit Design (Steinbeck Forum)
Chair: Vaughn Betz, University of Toronto
Automatic
Dmitry Burlyaev, Pascal Fradet, Alain Girault (INRIA & University Grenoble Alpes)
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200 MS/s ADC Implemented in a FPGA Employing TDCs
Harald Homulle (Delft University of Technology), Francesco Regazzoni (USI - ALaRI), Edoardo Charbon (Delft University of Technology)
Makoto Miyamura, Toshitsugu Sakamoto, Yukihide
Tsuji, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi,
Hiromitsu Hada
2:55pm |
Poster Session 4 (Colton Room) |
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11 posters (please refer to the list below) |
3:55 |
Session 8: Applications (Steinbeck Forum) |
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Chair: Kia Bazargan, University of Minnesota |
Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA
Ren Chen, Sruja Siriyal, Viktor Prasanna (University of Southern California, Los Angeles)
Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment
James Arram, Wayne Luk (Imperial College), Peiyong Jiang (The Chinese University of Hong Kong)
4:45pm Best Paper Award and Closing Remarks (Steinbeck Forum)
Deming Chen and George A. Constantinides
Posters
Poster Session 1:
An Efficient and Flexible FPGA Implementation of a Face Detection System Hichem Ben Fakih, Ahmed Elhossini, Ben Juurlink (Technical University of Berlin)
A Novel Method for Enabling FPGA
Alban Bourge, Olivier Muller, Frédéric Rousseau (University Grenoble Alpes)
FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation Based on the
Wentai Zhang, Li Shen (Peking University), Thomas Page (University of Bremen),
Guojie Luo (Peking University), Peng Li (University of California, Los Angeles), Peter Maaß (University of Bremen), Ming Jiang (Peking University), Jason Cong (University of California, Los Angeles)
Logic Gates in the Routing Network of FPGAs
Elias Vansteenkiste, Berg Severens, Dirk Stroobandt (Ghent University)
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Martinianos Papadopoulos (University of Cyprus), Christos Ttofis (ACC Innovations Ltd), Christos Kyrkou, Theocharis Theocharides (University of Cyprus)
Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion
An Automated Design Framework for Floating Point Scientific Algorithms Using Field Programmable Gate Arrays (FPGAs)
Michaela E. Amoo (Howard University), Youngsoo Kim, Vance Alford, Shrikant Jadhav, Naser I. El- Bathy, Clay S. Gloster (North Carolina A&T State University)
Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura (Fujitsu Laboratories Ltd.)
Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei (Tsinghua University)
Exploring Efficiency of Ring
Munich), Hamid Noori (Ferdowsi University of Mashhad), Farhad Mehdipour (Kyushu University)
Formal Verification ATPG Search Engine Emulator
Gregory Ford (IBM Microelectronic), Aswin Krishna (CWRU), Jacob A. Abraham (University of Texas, Austin), Daniel G. Saab (CWRU)
Ralf Salomon, Ralf Joost, Matthias Hinkfoth (University of Rostock)
Poster Session 2:
An
Yutaro Ishigaki, Ning Li, Yoichi Tomioka (Tokyo University of Agriculture and Technology), Akihiko Miyazaki (NTT Device Technology Laboratories),
Kitazawa Hitoshi (Tokyo University of Agriculture and Technology)
An FPGA Implementation of a
Yaoqiang Li, Pierce
A Parallel and Scalable
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A
FiT – An Automated Toolkit for Matching Processor Architecture to Applications
Charles Mutigwe (NxCORES Research), Johnson Kinyua (Virginia International University), Farhad Aghdasi (University of Fort Hare)
Naoto Nojiri, Lin Meng, Katsuhiro Yamazaki (Ritsumeikan University)
An FPGA Implementation of
Hitoshi Kitazawa (Tokyo University of Agriculture and Technology)
300 Thousand Gates Single Event Effect Hardened
REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography Bo Wang, Leibo Liu (Tsinghua University)
Architecture of
A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm Xianjian Zheng, Fan Zhang, Lei Chen, Zhiping Wen, Yuanfu Zhao, Xuewu Li
(Beijing Microelectronics Technology Institute)
A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture Junbin Wang, Leibo Liu, Jianfeng Zhu, Shouyi Yin, Shaojun Wei (Tsinghua University)
Poster Session 3:
Acceleration of Synthetic Aperture Radar (SAR) Algorithms Using Field Programmable Gate Arrays (FPGAs)
Youngsoo Kim, William Harding, Clay S. Gloster Jr. (North Carolina A&T State University), Winser Alexander (North Carolina State University)
An Embedded FPGA Operating System Optimized for Vision Computing Zhilei Chai, Jin Yu, Zhibin Wang, Jie Zhang (Jiangnan University),
Haojie Zhou (State Key Laboratory of Mathematical Engineering and Advanced Computing)
FPGA Implementation of Trained Coarse Carrier Frequency Offset Estimation and Correction for OFDM Signals
Marko Jacovic, James Chacko, Doug Pfeil, Nagarajan Kandasamy, Kapil R. Dandekar (Drexel University)
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Silicon Verification Using
Tomasz S. Czajkowski (Altera, Inc.)
A Hardware Implementation of a Unit for Geometric Algebra Operations with Parallel Memory Arrays
Gerardo Soria García, Adrian Pedroza de la Crúz, Susana Ortega Cisneros (CINVESTAV UGdl), Juan José Raygoza Panduro (CUCEI UdeG), Eduardo Bayro Corrochano (CINVESTAV UGdl)
Efficient Generation of Energy and Performance Pareto Front for FPGA Designs Sanmukh R. Kuppannagari, Viktor K. Prasanna (University of Southern California)
A Novel Coefficient Address Generation Algorithm for
Zhuo Qian, Martin Margala (University of Massachusetts Lowell)
RapidPath: Accelerating Constrained Shortest Path Finding in Graphs on FPGA
Chao Wang, Xi Li, Qi Guo, Xuehai Zhou (University of Science and Technology of China)
High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL
Nasibeh Nasiri, Oren Segal, Martin Margala (University of Massachusetts Lowell), Wim Vanderbauwhede (University of Glasgow), Sai Rahul Chalamalasetti (HP Servers)
Poster Session 4:
Bridging Architecture and Programming for
An Automatic Design Flow for Hybrid Parallel Computing on MPSoCs
Hongyuan Ding, Miaoqing Huang (University of Arkansas)
MedianPipes: An FPGA based Highly Pipelined and Scalable Technique for Median Filtering Umer I. Cheema (University of Illinois at Chicago), Gregory Nash (Altera Corporation), Rashid Ansari (University of Illinois at Chicago), Ashfaq A. Khokhar (Illinois Institute of Technology)
Toward Wave Digital Filter based Analog Circuit Emulation on FPGA
Wei Wu (University of California, Los Angeles), Peng Gu (Tsinghua University),
Optimized
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Area Optimization of Arithmetic Units by Component Sharing for FPGAs
Shao Lin Tang, Guy Lemieux (University of British Columbia)
Customizable and High Performance Matrix Multiplication Kernel on FPGA
Jie Wang (Tsinghua University), Jason Cong (University of California, Los Angeles)
Accelerating Complete Decision Support Queries Through
FPGA Acceleration of Irregular Iterative Computations Using
Optimizations
Siddhartha, Nachiket Kapre (Nanyang Technological University)
On Implementation of LUT with Large Numbers of Inputs
Masahiro Fujita (University of Tokyo)
Design of a Loeffler DCT Using Xilinx Vivado HLS
Seung Yeol Baik, Seokjin Jeong (Korea University),
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